1 standard products ut28f64 radiation-hardened 8k x 8 prom data sheet august 2001 features q programmable, read-only, asynchronous, radiation- hardened, 8k x 8 memory - supported by industry standard programmer q 35ns and 45ns maximum address access time (-55 o c to +125 o c) q ttl compatible input and ttl/cmos compatible output levels q three-state data bus q low operating and standby current - operating: 100ma maximum @28.6mhz derating: 3ma/mhz - standby: 500 m a maximum (post-rad) q radiation-hardened process and design; total dose irradiation testing to mil-std-883, method 1019 - total dose: 1e6 rad(si) - let th (0.25) ~ 100 mev-cm 2 /mg - sel immune > 128 mev-cm 2 /mg - saturated cross section cm 2 per bit, 1.0e-11 - 1.2e-8 errors/device-day, adams 90% geosynchronous heavy ion - memory cell let threshold: >128 mev-cm 2 /mg q qml q & v compliant part - ac and dc testing at factory q packaging options: - 28-pin 100-mil center dip (0.600 x 1.4) - 28-lead 50-mil center flatpack (0.490 x 0.74) q v dd : 5.0 volts + 10% q standard microcircuit drawing 5962-96873 product description the ut28f64 amorphous silicon anti-fuse prom is a high performance, asynchronous, radiation-hardened, 8k x 8 programmable memory device. the ut28f64 prom features fully asychronous operation requiring no external clocks or timing strobes. an advanced radiation-hardened twin-well cmos process technology is used to implement the ut28f64. the combination of radiation- hardness, fast access time, and low power consumption make the ut28f64 ideal for high speed systems designed for operation in radiation environments. decoder memory array sense amplifier programming control logic dq(7:0) a(12:0) ce pe oe figure 1. prom block diagram
2 device operation the ut28f64 has three control inputs: chip enable ( ce ), program enable ( pe ), and output enable ( oe ); thirteen address inputs, a(12:0); and eight bidirectional data lines, dq(7:0). ce is the device enable input that controls chip selection, active, and standby modes. asserting ce causes i dd to rise to its active value and decodes the thirteen address inputs to select one of 8,192 words in the memory. pe controls program and read operations. during a read cycle, oe must be asserted to enable the outputs. pin names table 1. device operation truth table 1 notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not re commended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. test per mil-std-883, method 1012, infinite heat sink. nc a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss v dd pe nc a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a(12:0) address ce chip enable oe output enable pe program enable dq(7:0) data input/data output oe pe ce i/o mode mode x 1 1 three-state standby 0 1 0 data out read 1 0 0 data in program 1 1 0 three-state read 2 symbol parameter limits units v dd dc supply voltage -0.3 to 7.0 v v i/o voltage on any pin -0.5 to (v dd + 0.5) v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.5 w t j maximum junction temperature +175 c q jc thermal resistance, junction-to-case 2 3.3 c/w i i dc input current 10 ma
3 recommended operating conditions dc electrical characteristics (pre/post-radiation)* (v dd = 5.0v 10%; -55 c < t c < +125 c) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 1.0e6 rads(si). 1. measured only for initial qualification, and after process or design changes that could affect input/output capacitance. 2. supplied as a design limit but not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. 4. functional test. 5. derates at 2.5ma/mhz. symbol parameter limits units v dd positive supply voltage 4.5 to 5.5 v t c case temperature range -55 to +125 c v in dc input voltage 0 to v dd v symbol parameter condition minimum maximum unit v ih high-level input voltage (ttl) 2.4 v v il low-level input voltage (ttl) 0.8 v v ol1 low-level output voltage i ol = 4.8ma, v dd = 4.5v (ttl) 0.4 v v ol2 low-level output voltage i ol = 200 m a, v dd = 4.5v (cmos) v ss + 0.05 v v oh1 high-level output voltage i oh = -400 m a, v dd = 4.5v (ttl) i oh = -2.0ma 2.4 3.5 v v oh2 high-level output voltage i oh = -200 m a v dd = 4.5v (cmos) i oh = -100 m a 4.45 v dd - 0.3 v c in 1 input capacitance | = 1mhz, v dd = 5.0v 15 pf c io 1, 4 bidirectional i/o capacitance | = 1mhz, v dd = 5.0v v out = 0v 15 pf i in input leakage current v in = 0v to v dd -1 1 m a i oz three-state output leakage current v o = 0v to v dd v dd = 5.5v oe = 5.5v -10 10 m a i os 2,3 short-circuit output current v dd = 5.5v, v o = v dd v dd = 5.5v, v o = 0v -90 90 ma ma i dd (op) 5 supply current operating @28.6mhz (35ns product) @22.2mhz (45ns product) ttl input levels (i out = 0), v il = 0.2v v dd , pe = 5.5v 100 85 ma i dd (sb) post-rad supply current standby cmos input levels , v il = v ss to 0.25v ce = v dd -025, v ih = v dd -0.25v 500 m a
4 read cycle a combination of pe greater than v ih (min), and ce less than v il (max) defines a read cycle. read access time is measured from the latter of device enable, output enable, or valid address to valid data output. an address access read is initiated by a change in address inputs while the chip is enabled with oe asserted and pe deasserted. valid data appears on data output, dq(7:0), after the specified t avqv is satisfied. outputs remain active throughout the entire cycle. as long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time. the chip enable-controlled access is initiated by ce going active while oe remains asserted, pe remains deasserted, and the addresses remain stable for the entire cycle. after the specified t elqv is satisfied, the eight-bit word addressed by a(12:0) appears at the data outputs dq(7:0). output enable-controlled access is initiated by oe going active while ce is asserted, pe is deasserted, and the addresses are stable. read access time is t glqv unless t avqv or t elqv have not been satisfied. ac characteristics read cycle (post-radiation)* (v dd = 5.0v 10%; -55 c < t c < +125 c) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 1.0e6 rads(si). 1. functional test. 2. three-state is defined as a 400mv change from steady-state output voltage. symbol parameter 28f64-35 min max 28f64-45 min max unit t avav 1 read cycle time 35 45 ns t avqv read access time 35 45 ns t axqx 2 output hold time 0 0 ns t glqx 2 oe -controlled output enable time 0 0 ns t glqv oe -controlled access time 15 15 ns t ghqz oe -controlled output three-state time 15 15 ns t elqx 2 ce -controlled output enable time 0 0 ns t elqv ce -controlled access time 35 45 ns t ehqz ce -controlled output three-state time 15 15 ns
5 radiation hardness the ut28f64 prom incorporates special design and layout features which allow operation in high-level radiation environments. utmc has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. for transient radiation hardness and latchup immunity, utmc builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub cmos process. in addition, utmc pays special attention to power and ground distribution during the design phase, minimizing dose-rate upset caused by rail collapse. radiation hardness design specifications 1 note: 1. the prom will not latchup during radiation exposure under recommended operating conditions. figure 2. prom read cycle t avav t avqv t elqv t glqv t avqv t axqx t ehqz t ghqz a(12:0) ce oe dq(7:0) t glqx t elqx total dose 5.0e5 rad(si) latchup let threshold >128 mev-cm 2 /mg memory cell let threshold >128 mev-cm 2 /mg transient upset let threshold 54 mev-cm 2 /mg transient upset device cross section @ let=128 mev-cm 2 /mg 1e-6 cm 2
6 notes: 1. 50pf including scope probe and test socket. 2. measurement of data output occurs at the low to high or high to low transition mid-point (ttl input = 1.5v). 90% figure 3. ac test loads and input waveforms input pulses 10% < 5ns < 5ns ttl 0v 3.0v 330 ohms v ref =1.73v 50pf 90% 10%
7 figure 4. 28-pin 100-mil center dip (0.600 x 1.4) notes: 1. seal ring to be electrically isolated. 2. all exposed metalized areas to be plated per mil-prf-38535. 3. ceramic to be opaque. 4. dimension letters refer to mil-std-1835. d 1.400 0.020 pin no. 1 id. s1 0.005 min. s2 0.005 min. e 0.595 0.015 e1 0.600 c 0.010 a 0.175 max. l 0.200 0.125 e 0.100 b 0.018 .002 q 0.060 0.015 top view end view b 0.065 0.045 side view
8 notes: 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in accordance with mil-prf-38535. 4. dimension letters refer to mil-std-1835. 5. lead position and coplanarity are not measured. 6. id mark symbol is vendor option. 7. with solder, increase maximum by 0.003. figure 5. 28-lead 50-mil center flatpack (0.490 x 0.74) 0.015 0.008 0.015 0.008 pin no. 1 id. 6 26 places 0.050 bsc e d 0.740 max e1 0.550 max 5 -b- 7 s1 (4) places 0.000 min. 7 -d- -c- a 0.115 0.045 0.045 0.026 l 0.370 0.250 e2 0.180 min e3 0.030 min e 0.520 0.460 -h- c 0.009 0.004 0.040 0.022 0.015 28 places -a- h a-b d 5 s s 0.010 m h a-b d 5 s s m 0.036 top view end view b k k q
9 ordering information 64k prom: smd lead finish: (a) = solder (c) = gold (x) = optional case outline: (x) = 28-pin dip (y) = 28-lead flatpack class designator: (q) = class q (v) = class v device type (01) = 35ns access time, ttl inputs, cmos/ttl compatible outputs (02) = 45ns access time, ttl inputs, cmos/ttl compatible outputs drawing number: 96873 total dose: (g) = 5e5 rads(si) (f) = 3e5 rads(si) (r) = 1e5 rads(si) federal stock class designator: no options 5962 * 96873 * * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. 4. lead finish: factory programming either solder or gold. field programming gold only.
10 64k prom ut **** * ** - * * * * * * total dose: ( ) = none lead finish: (a) = solder (c) = gold (x) = optional screening: (c) = mil temp (p) = prototype package type: (p) = 28-lead dip (u) = 28-lead flatpack access time: (35) = 35ns access time, ttl compatible inputs, cmos/ttl compatible outputs (45) = 45ns access time, ttl compatible inputs, cmos/ttl compatible outputs device type modifier: (t) = ttl compatible inputs and cmos/ttl compatible outputs device type: (28f64) = 8kx8 one time programmable prom notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. military temperature range flow per utmc manufacturing flows document. radiation characteristics are neither tested nor guarante ed and may not be specified. 4. prototype flow per utmc manufacturing flows document. devices have prototype assembly and are tested at 25 c only. radiation characteristics are neither tested nor guaranteed and may not be specified. lead finish is gold only. 5. lead finish: factory programming either solder or gold. field programming gold only.
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